This invention relates generally to computer systems, and more particularly to the access of memory modules directly connected to a system bus of a computer system.
As it is known in the art, computer systems generally include at least one central processing unit (CPU) module, a main memory for storing data, at least one input/output (I/O) module, and a system bus coupling the aforementioned devices to the CPU module. The system bus typically includes data, address, and control lines.
Often, the main memory includes a plurality of memory modules each having an interface connected to the system bus. Each memory module contains semiconductor chips having a predetermined number of memory cells. The chips are often referred to as RAM, Random Access Memory, or DRAM, Dynamic Random Access Memory, in that each storage location is randomly addressable as distinguished from other types of memory devices such as magnetic tape or disk which are sequentially accessible, in that a number of storage locations are scanned before reaching the desired addressed location.
As an example, a 64 K memory chip has 216 or 65,536 addressable storage locations. Each storage location contains one memory cell which stores one binary bit of data.
The address range of the computer system is determined primarily by the number of address lines that are provided on the system bus. An address range of 0-64 K requires 216 permutations of 16 binary bits. Increasing the address bus by one line effectively doubles the previous address range of the system.
It should be noted that although memory capacity is related to the size of the address range, it is not the same as the address range. Most memory modules store multiple bytes of data at each addressable location. Thus, memory capacity is a function of the number of addressable locations (i.e., address range) and the amount of data stored at each location.
Generally each memory module responds to a different address range within the overall address range of the computer system. The size of each module""s address range corresponds to the number of addressable locations on the module. The starting address of a module""s address range may be determined by virtue of the position (i.e., backplane slot) in which the module is placed within the computer system, if each module has the same capacity, or the starting address may be assigned through the use of memory configuration software and hardware which determines the number of addressable locations of each memory module in the system prior to assigning address ranges.
CPUs, as well as other commander modules such as the I/O module, are capable of initiating transactions (i.e., read or write) to main memory on the system bus. In order to initiate a transaction on the system bus, a CPU must first gain control of the system bus which is often accomplished by arbitrating for the bus. Once the CPU has gained control of the system bus, the CPU drives an address and a command. If the command is a write to main memory, the CPU will also drive data.
The address driven indicates a location in main memory which the CPU wishes to read data from or write data to. Typically, when an address is driven, each memory module decodes the address to determine if the address being driven is within its address range such that it should respond.
There are often times when a memory module will be inaccessible because it is busy (i.e., unavailable) with another task, such as a memory refresh. Additionally, a memory module may be unavailable for a period of time following a write to main memory. Once the CPU transfers the data to the memory module, the transaction is complete and the system bus can be used by another module to initiate a transaction. However, the memory module generally requires additional time to complete the actual write of the data into the RAMs. Thus, if a subsequent read or write transaction is directed to the same memory module, the memory module may be unavailable and unable to respond.
A memory module may also be busy with another commander module""s transaction in a computer system supporting a pipelined system bus. A pipelined system bus allows commander modules to initiate transactions with target modules, for example, memory modules, and then release the system bus such that it may be used by other modules. Subsequently, the target will gain control of the system bus and complete the earlier initiated transaction. In such a system, a first commander may initiate a transaction with a particular memory module and then release the system bus which is immediately controlled by a second commander. Where the second commander initiates a transaction with the same memory module, the memory module will be busy with the first commander""s transaction, and thus, unavailable.
Many different techniques have been designed to handle unavailable memory modules, including having the CPU wait on the system bus until the memory module can respond or having the CPU release the system bus and retry the transaction at a later time. However, having the CPU wait on the system bus increases the time it takes to complete a transaction, prevents other commander modules from using the system bus for useful transactions (i.e., transactions which would complete). Furthermore, hardware must be designed to handle such unavailable conditions.
On the other hand, some techniques attempt to avoid a memory unavailable situation. For example, many computer systems partition the memory devices (i.e., RAM) of each memory module into multiple banks. The access circuitry of each bank responds to a different range of addresses allowing each bank to be independently accessed. Further, each bank has its own read and write circuitry such that each bank is entirely independent with the exception that each bank shares the memory module""s system bus interface logic. The independent nature of the banks allows a write to a first bank to be followed immediately by a read or write to a second bank without having to wait for the write to the first bank to complete even when both banks are on the same memory module. Partitioning a memory module""s addressable locations into independent banks increases the possibility that subsequent transactions will be to different banks, thus, reducing the number of times a CPU may have to wait or retry a memory access. However, an access by a first commander to a memory bank immediately followed by an access of the same memory bank by a second commander in a pipelined computer system will still result in a memory unavailable situation.
Another method which reduces the possibility of sending subsequent transactions to the same memory bank is to interleave memory. Interleaving is the practice of storing data in consecutive memory locations in alternating or successive memory banks. In a conventional 2-way interleaved memory, there is an xe2x80x9cevenxe2x80x9d memory bank and an xe2x80x9coddxe2x80x9d memory bank for each range of addresses. Any two sequential memory locations are stored in different memory banks. If two transactions access two sequential memory locations, the operation is as follows: the first location is written, for example, in a first memory bank and the second location is read, for example, from a second memory bank. Thus, since two sequential locations will be in different banks, they can be accessed very quickly without waiting for a write to complete. Other multiple way interleaving (i.e., 4-way, 8-way, etc.) may also be implemented.
The interleaved memory technique is based on the premise that there is a reasonably high probability that sequential accesses to memory will be in successive memory locations. Thus, sequential memory locations are placed in different banks so that they can be accessed quickly. The possibility remains, however, that sequentially issued transactions will be directed at the same memory bank with the result that a subsequent transaction will encounter an unavailable memory bank.
Another technique which avoids sending transactions to a memory bank which is unavailable is to have all commander modules (i.e., all modules capable of issuing transactions directed at main memory) decode addresses sent on the system bus by all other modules to determine and track which memory banks are in use. A CPU trying to access main memory first decodes the address of the bank to be accessed. The CPU then determines whether that memory bank is in use. If the bank is in use, the CPU will not attempt to gain control of the system bus in order to issue the transaction, and if the bank is not in use, then the CPU will attempt to gain control of the system bus and issue the transaction.
There are circumstances, however, which will not always allow a commander module to determine if the memory bank it needs to access is in use (i.e., unavailable). For example, tracking which memory banks are being accessed by other commander modules does not determine whether the memory bank is executing a memory refresh cycle. Further, a previous commander module may have issued a write transaction, and thus, although the previous commander is no longer accessing the memory bank, the memory bank is busy completing the write of the data into the RAMs.
In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are memory modules which have at least one memory bank in which data is stored in addressable locations. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank available signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus, where a commander module is a module capable of initiating transactions on the system bus. Each commander module includes logic, responsive to the memory bank available signals, for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.
In accordance with the invention, a memory bank available signal associated with a memory bank will indicate that the memory bank is unavailable when a commander module accesses the memory bank. Further, where the access is a write of data to the memory bank, the memory bank available signal will reflect an unavailability status until the data is written into the memory bank. In accordance with another aspect of the invention, an unavailability status will be indicated prior to and during the execution of a memory refresh cycle on the memory bank.
In accordance with another further aspect of the invention, the control signals further include memory bank identification signals. Each of the memory banks are responsive to a predetermined value driven on the memory bank identification signals and respond to transactions initiated by commander modules on the system bus, when the predetermined value is driven on the memory bank identification signals. Further, the commander modules include logic for providing the memory bank identification signals with values which correspond to the memory bank they seek to access and logic for using the memory bank identification signals and the memory bank available signals to determine if the memory bank they seek to access is available. With such an arrangement, the memory bank access time is reduced when the memory bank uses the memory bank identification bits as opposed to the full address bus to determine if it is the target. Further, flexible memory addressing and interleaving are permitted through the commander module logic used to provide values on the memory bank identification signals.